Our present invention relates generally to field effect transistors and, more particularly, to an enhancement mode or normally-off junction field effect transistor.
Gallium arsenide (GaAs) junction and Schottky barrier field effect transistors (FETs) have demonstrated useful application in microwave amplifier design at frequencies beyond the reach of silicon bipolar and unipolar transistors. The high-speed integrated logic performance of GaAs Schottky barrier field effect transistors, which are operated in the normally-on state, in integrated logic gate design revealed a 60 to 100 picosecond (ps) propagation delay with an average power dissipation of 90 milliwatts (mW), for example.
GaAs enhancement mode (or normally-off) field effect transistor integrated circuits offer better speed-power products than complementary metal oxide semiconductor (CMOS) or Schottky-clamped bipolar ones at operating frequencies of 1 megahertz (MHz) and above. Optimized devices are theoretically capable of operation with a speed-power product of 2 pico joules (pJ), achieving a switching speed of 1 nanosecond (ns) at a power dissipation of 2 mW per gate. The temperature range from 2.degree. to 650.degree.K. for the GaAs junction field effect transistors (JFETS) encompasses applications which are not possible with silicon devices.
In addition, completed radiation testing revealed that GaAs JFETS and integrated circuits recover very rapidly from ionizing radiation pulses, undergo small degradations due to high neutron fluences and are immune to high total gamma doses, and therefore can be used in hardened electronic systems which are required to operate in nuclear environments too severe for silicon devices.
It may be noted that the general configuration of the enhancement mode or normally-off junction field effect transistor of this invention is somewhat similar to that of the single gate field effect transistor disclosed in the patent application of Rainer Zuleeg, Ser. No. 811,154 filed Mar. 27, 1969 for Multichannel Field-Effect Transistor and Process. The enhancement mode JFET, however, is physically different and involves specific critical parameters distinguishing the device from the prior single gate FET. Thus, the enhancement mode JFET is of an unobvious design having characteristics not predictable by standard FET theory.